Integrated circuit (IC) technology has continually advanced in the last few decades. In doing so, ICs have enabled a variety of applications ranging from smart consumer electronic devices to interplanetary communication. Interestingly, advances in ICs have also resulted in a dramatic reduction in cost of individual IC components. This reduction in cost is enabled by the ability of modern IC fabrication technology to produce increasingly large number of IC components on a single semiconductor wafer.
A couple of factors play an indispensable role in setting the trend of continuous IC advancements. Firstly, in what is known as node scaling, the size of the components of ICs are shrinking with each next generation technology node. This means that an increasingly large number of components can be fabricated on a single wafer. Remarkably, the shrinking of components also enable a significant increase in IC performance. Secondly, the size of semiconductor wafers continually increase to accommodate an increasingly more number of components on a single wafer. Together, the two factors allowed IC components to be mass produced at increasingly large scales.
Although modern semiconductor fabrication has enabled mass production of ICs, the produced ICs are useful only if they are functional. The ratio of the number of ICs that meet performance specifications to the total number of produced ICs is called yield, an important quantity that semiconductor fabs strive to maximize. Yield maximization leads to reduction in unit cost of IC. However, maximizing yield is a formidable task because of the exhaustive number and complexity of process steps involved in IC fabrication. The fabrication of ICs typically involves hundreds of process steps where a semiconductor wafer is subjected to steps such as ion implantation, deposition, lithography, etching, and polishing. Together, these steps fabricate intricate nanometer scale structures in ICs. Because of the exhaustive nature of IC fabrication, it is difficult to use data from functional tests of ICs to associate a failure in IC functionality to an abnormality in a particular process step. Nevertheless, knowing precisely where the abnormality occurred is crucial for maximizing yield. Accordingly, wafer inspection tools are employed after every significant process step to inspect for the presence of abnormalities or defects. If an increased number of defects are observed at a particular stage of fabrication, efforts are undertaken to identify the root cause of defects and to eliminate the root cause. Containing the root cause of defects quickly would prevent defects from affecting multiple wafers, thereby minimizing the impact on yield. Therefore, yield maximization is dependent on: a) ability of wafer inspection tools to detect defects, and b) effectively eliminating the source of defects.
Unfortunately, advances in semiconductor fabrication have made it very difficult to maximize yield. This is primarily because of the inability of wafer inspection tools to detect increasingly small yield-affecting defects. As the size of structures in ICs shrink due to node scaling, increasingly small defect sizes become problematic. In other words, the probability of a 14 nm defect to affect yield is substantially higher in a 14 nm technology node than in a 22 nm node. In order to maintain yield in a next generation technology node, the defect sensitivity of wafer inspection tools must follow the node scaling factor of the next generation technology node. In other words, if a next generation technology node shrinks by a factor of 1.5× with respect to a previous generation technology node, defect sensitivity of wafer inspection tools will also need to shrink by 1.5× in order for the next generation node to maintain the same yield as the previous generation node. However, in hindsight, it is discomforting to notice that the defect sensitivity of wafer inspection tools have been significantly lagging behind node scaling. In the last ten years, while the smallest IC structures shrank from 130 nm to 14 nm (over 9× reduction), defect sensitivity improved at a substantially slower rate from 50 nm to 20 nm (2.5× reduction). For the 130 nm technology node, defect sizes 2.6× smaller than the node size were detected. However, for the 14 nm technology node, wafer inspection tools are unable to even detect defects sizes 1× the node size. As a result, an increasing number of yield affecting defects pass undetected through wafer detection systems, leading to a significant negative impact in yield.
There are two fundamental reasons for the inability of wafer inspection tools to match up to the fast pace of node scaling. Firstly, the intensity of light scattered by defects decreases exponentially as the size of defect decreases. A 2× reduction in defect size leads to a 64× reduction in scattered light intensity. As a result, photodetectors used in wafer inspection tools receive exponentially smaller radiation levels from small defect sizes. Secondly, surface roughness present in wafer creates an undesirable background radiation called haze, which overwhelms scattered radiation from small defects. Traditional wafer inspection tools strive to maximize defect sensitivity by reducing the wavelength of incident light and increasing the power of incident light. However, doing so not only increases scattered radiation from defects but also increases haze. Furthermore, higher power beams with shorter wavelengths have the potential to induce a permanent damage to a semiconductor wafer.
Traditional wafer inspection suffers from a number of problems: a) reduced sensitivity; b) reduced scattering intensity for small defects; c) background scatting due to surface roughness; d) low signal to background ratios; e) need for a high power laser beam; and f) need for increasingly short wavelength laser beams.
Accordingly, there is a need for an improved wafer inspection that can improve sensitivity; increase scattering intensity for small defects; reduce background scattering due to surface roughness; increase signal to background ratios; relax the need for a high power laser beam; and relax the need for shorter wavelength laser beams.